1. Field of the Invention
The present invention relates to a semiconductor memory device and, more specifically, to a semiconductor memory device containing a cache memory in which a cache memory is integrated on the same chip.
2. Description of the Background Art
A main memory included in a computer system is formed of a dynamic random access memory (hereinafter referred to as DRAM) which has large capacity and slow speed of operation and is not very expensive. In order to improve cost-efficiency of the computer system, a high speed memory having smaller capacity is often provided as a high speed buffer between the main memory and a central processing unit (hereinafter referred to as CPU). The high speed buffer is called a cache memory. Blocks of data which are considered to be frequently used by the CPU are copied from the main memory and stored in the cache memory. If the data stored in an address which is to be accessed in the DRAM by the CPU also exist in the cache memory, it is called a cache hit. The CPU accesses the high speed cache memory to take the necessary data from the cache memory. Meanwhile, if the data stored in the address to be accessed by the CPU in the DRAM do not exist in the cache memory, it is called a cache miss. In that case, the CPU accesses the low speed main memory, takes the necessary data from the main memory and transfers a block including the data from the DRAM to the cache memory.
However, such a cache memory requires an expensive high speed memory. Therefore, it can not be used in a compact computer system in which lower cost is given priority. Therefore, a simple cache system has been formed by utilizing a page mode or a static column mode included in a general purpose DRAM.
FIG. 9 is a block diagram showing a basic structure of a conventional DRAM device in which a page mode or a static column mode is possible.
Referring to FIG. 9, a plurality of word lines and a plurality of bit line pairs are arranged intersecting with each other in a memory cell array 50, and memory cells are provided at respective intersections. In FIG. 9, one word line WL, one bit line pair BL, BL, and one memory cell MC provided at the intersection of the word line WL and the bit line BL are shown as representatives.
Word lines in the memory cell array 50 are connected to a row decoder 53 through a word driver 52. Bit line pairs in the memory cell array 50 are connected to a column decoder 56 through a sense amplifier portion 54 and an I/O switch 55. A multiplexed signal MPXA in which a row address signal RA and a column address signal CA are multiplex is applied to the row address buffer 57 and the column address buffer 58. The row address buffer 57 applies a row address signal RA to the row decoder 53, and the column address buffer 58 applies a column address signal CA to the column decoder 56. Meanwhile, an output buffer 59 and an input buffer 60 are connected to the I/O switch 55.
Waveforms of operation in a common reading cycle, a page mode cycle and a static column mode cycle of the DRAM device are shown in FIGS. 10A, 10B and 10C, respectively. In the common reading cycle shown in FIG. 10A, first the row address buffer 57 takes the multiplexed address signal MPXA at a falling edge of a row address strobe signal RAS to apply the same as the row address signal RA to the row decoder 53. The row decoder 53 selects one of the plurality of word lines in response to the row address signal RA. The selected word line is activated by the word driver 52. Consequently, information stored in the plurality of memory cells connected to the word line is read to the corresponding bit lines, and the information is detected and amplified in the sense amplifier portion 54. At this time, information of memory cells of one row is latched in the sense amplifier portion 54.
Thereafter, the column address buffer 58 takes the multiplexed address signal MPXA at a falling edge of a column address strobe signal CAS to apply the same as the column address signal CA to column decoder 56. The column decoder 56 selects one of the information of one row latched in the sense amplifier portion 54 in response to the column address signal CA. The selected information is taken outside as output data Dout through the I/O switch 55 and the output buffer 59.
The access time (RAS access time) t.sub.RAC in this case corresponds to the time period from the falling edge of the row address strobe signal RAS until the-output data Dout becomes effective. The cycle time t.sub.C is a sum of the time in which the device is active and the time of RAS precharge t.sub.RP. As a standard value, t.sub.C is about 200 ns when t.sub.RAC =100 ns.
In the page mode cycle and the static column mode cycle shown in FIGS. 10B and 10C, memory cells on the same row are accessed by changing the column address signal CA. In the page mode cycle, the column address signal CA is latched at the falling edge of the column address strobe signal CAS. In the static column mode cycle, access is done only by the change of the column address signal CA as in the static RAM (SRAM).
The CAS access time t.sub.CAC in the page mode cycle and the address access time t.sub.AA in the static column mode cycle are approximately 1/2 of the RAS access time t.sub.RAC, which is about 50 ns when t.sub.RAC =100 ns. In these cases, the cycle time also becomes shorter, and in the page mode cycle, it becomes about 50 ns as in the static column mode cycle, although it depends on the value of CAS precharge time t.sub.CP.
FIG. 11 is a block diagram showing a structure of a simple cache system utilizing the page mode or the static column mode of the DRAM device shown in FIG. 9. FIG. 12 shows waveforms of operation of the simple cache system shown in FIG. 11.
Referring to FIG. 11, a main memory 21 is formed to have 1M byte by 8 DRAM devices 20, having 1M.times.1 bit structure. In this case, 20 (2.sup.20 =1048576=1M) address lines are necessary before the row address signal and the column address signal are multiplexed. However, since the row address signal RA and the column address signal CA are multiplexed by the address multiplexer 22, the number of the address lines actually connected to each DRAM devices 20 is 10.
The operation of the simple cache system shown in FIG. 11 will be described with reference to the waveforms of operation of FIG. 12.
First, 20 bits of address signals AD corresponding to the data necessary for the CPU 24 are generated by an address generator 23. A latch (tag) 25 maintains row address signals corresponding to the data selected in the last cycle. A comparator 26 compares 10 bits of row address signals RA out of the 20 bits of address signals AD with the row address signals maintained in the latch 25. If they coincide with each other, it means that the same row as in the last cycle is accessed in the present cycle. This is called a cache hit. In that case, the comparator 26 generates a cache hit signal CH.
A state machine 27 carries out a page mode control in which the column address strobe signal CAS is toggled while the row address strobe signal RAS is kept at a low level, in response to the cache hit signal CH. On this occasion, an address multiplexer 22 applies a column address signal CA to the DRAM devices 20 (see FIG. 12). Consequently, data corresponding to the column address signal CA is taken out of the data latched in the sense amplifier portion of each DRAM device 20. In this manner, when a cache hit occurs, output data can be provided at high speed with the access time t.sub.CAC from each DRAM device 20.
Meanwhile, if the row address signal RA generated from the address generator 23 does not coincide with the row address signal maintained in the latch 25, it means that the row accessed in the present cycle is different from that in the last cycle. It is called a cache miss.
In that case, the comparator 26 does not generate the cache hit signal CH. The state machine 27 carries out RAS/CAS control of a common reading cycle, and the address multiplexer 22 successively applies a row address signal RA and the column address signal CA to each DRAM device 20 (see FIG. 12). In this manner, when a cache miss occurs, a common reading cycle starting from precharging by the row address strobe signal RAS is started, the output data is provided slowly with the access time t.sub.RAC. Therefore, the state machine 27 generates a wait signal Wait to set the CPU 24 in a wait state. When a cache miss occurs, the new row address signal RA is maintained in the latch 25.
In the simple cache system of FIG. 11, data of one row (1024 bits, when 1M.times.1 bit DRAM device is used) of each array block in each DRAM device 20 are latched as one data block in the sense amplifiers. Therefore, the size of the data block is larger than needed, which causes a shortage of the numbers of data blocks (entry numbers) maintained in the latch (tag) 25. For example, in the simple cache system shown in FIG. 11, the entry number is 1. Therefore, the rate of cache hit (cache hit rate) is low.
Recently, DRAM devices having memory capacity of 16M bit on 1 chip have come to be manufactured. It will make it possible to provide the whole capacity of the main memory by, 1 chip in a personal computer system or the like. In view of the foregoing, the number of parts will be increased at interfaces or the like when the conventional standard DRAM devices are used in incorporating to the memory system, which will generate problems such as delay of signal transfer, which is fast enough in the chip, due to the delay between chips.
Japanese Patent Laying Open No. 62-38590 discloses a semiconductor memory device in which a DRAM, an SRAM and means for transferring data of 1 row at one time between those memories on 1 chip are provided. In the semiconductor memory device, one row of the DRAM is 1 block, so that the size of the data block is larger than needed. Consequently, the number of blocks maintained in the tag portion (the number of entries) becomes smaller, and the cache hit rate becomes lower. Further, SRAM cells are provided for respective bit line pairs of the DRAM and the SRAM serving as the cache memory is in the DRAM array, and accordingly the access speed is low. The speed of access is approximately the same as the access speed when the static column mode or the first page mode of the DRAM is used.